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HyperLynx Input/Output File Types
The following is a summary of the HyperLynx HyperSuite,
version 6.1 file types and extensions.
This information is useful for determining the compatibility of
HyperLynx I/O file formats with other software package applications as well as
for the maximum utilization of resident file types.
HyperLynx BoardSim reads .HYP (HyperLynx format) ASCII files. The .HYP file contains Printed
Circuit Board (PCB) layout information that is relevant to signal integrity
BoardSim automatically creates a .PJH file, a project file named after
the board, schematic, or multiple board project.
HyperLynx supports IBIS 3.2 Models in both LineSim and BoardSim. The extension
is .IBS. Many of the IBIS
features required for the latest microprocessors and other advanced ICs are
supported, including: Driver Schedule, Bus Hold, Dynamic Clamp and Electrical
Board Description (.EBD). EBD is
a high-quality simulation model for modules and other small boards without
revealing physical details. Models may also be created from a .HYP
Databook (.MOD) format - this is a HyperLynx (now part of Innoveda) proprietary
format, based on "databook" parameters. HyperSuite EXT includes a form-based dialog box that generates .MOD
models from data-sheet parameters. MOD models are non-linear and include curve
shaping and diode effects. MOD models
usually sacrifice little in accuracy compared to IBIS models and are easier to
create. These models usually represent
an entire family of ICs. For example, the 74ACXX: GATE model in GENERIC.MOD
represents the output of any non-line-driver 74AC IC.
Package-model library (.PML) format is an extension of the .MOD
format and adds package parasitics and component - specific pinouts. Innoveda supplies more than 5000 models in .PML
format. Automatic updating of the Model
Finder database allows database customization
include models not shipped in the HyperLynx product library (e.g., models
obtained from a semiconductor vendor).
Back annotate changes can be made in BoardSim to Innoveda's PowerPCB,
PowerLogic, and ViewDraw products. BoardSim can back annotate design changes,
including passive component values, IC models assigned by the .REF IC
AutoMapping file, and Quick Terminators (new virtual components). The design
changes are written to an ASCII ECO file formatted for PowerPCB, PowerLogic, or
ViewDraw. BoardSim can also dynamically
back annotate the changes to a running copy of PowerPCB or PowerLogic (the
changes appear in the target products almost immediately after back annotation
The .QPL (qualified parts list) IC AutoMapping file feature saves
considerable time on devices that are used across multiple designs. A single model mapping can apply to all of
the .HYP files that are being used.
The .QPL IC AutoMapping file maps the corporate part names to IC
models. In contrast, the .REF IC
AutoMapping file maps board-specific reference designators to models. The .QPL
file can be used with a .REF file, or by itself. It is also possible to have multiple .QPL
8. LineSim and BoardSim have an option to write SPICE
netlists (including coupling data), so that you can conveniently export to
SPICE and simulate in it. SPICE Writer,
available as an option in LineSim and in BoardSim, automatically generates a
SPICE-netlist output file containing a complete description of a schematic
(LineSim) or selected net (BoardSim), using SPICE transmission-line elements.
This output file also contains the passive components for the selected net, and
comment lines listing the drivers and receivers, for which the user can then
provide SPICE models. The output file
from SPICE Writer is created as a SPICE sub circuit. The output for an
uncoupled net is generated using standard SPICE "T" elements for
transmission lines, and should be compatible with most SPICE simulators. The
output for coupled nets is formatted specifically for Hspice, since there is no
industry-standard format for coupled nets; it uses the Hspice "W"
BoardSim supports the following PCB-layout tools (this list is subject to
change): Accel EDA / P-CAD, Cadence
Allegro, Mentor BoardStation and Veribest, Innoveda PowerPCB, (formerly PADS), Zuken CR-3000 / 5000, and
Zuken-Redac Visula / Cadstar for Windows.
Translators for Protel Advanced PCB and OrCAD Layout were included as
menu selections from these layout tools.
The Board Wizard has two types of files for analysis results to be used in
("Comma Separated Values") file - contains all of the report's
net-by-net data that can be read directly into Microsoft Excel or other
spreadsheet/database programs. For
example, export of oscilloscope waveforms may be done in .CSV format to
other programs like Microsoft Excel, other spreadsheets, or mathematics
software (e.g., Mathcad).
("Standard Delay Format") file - contains the pin-delay information
in the report file that can be read into Verilog and VHDL simulators, or other